1. Field of the Invention
This invention relates to data storage subsystems employing multiple caches and/or multiple non-volatile storage elements interposed between one or more host processors and a secondary storage device. More particularly this invention provides a convenient and efficient method and architecture for managing these multiple elements based upon their operability.
2. Description of the Related Art
Over the past few years, cache, or high density electronic storage has been introduced into DASD storage subsystems. Access time between the cache and the channel is much faster than that between DASD and the channel. There are various physical device movements and other operations associated with DASD which limit data transmission speed which are eliminated by caching. One such limitation is the time required for the magnetic disk to rotate until it is aligned with the transducer contained in the read head. Another is the limited bandwidth associated with the magnetic transducers used to read and write data.
These limitations are not present with a cache access. Through the use of various caching algorithms, frequently used data is maintained in cache storage rather than being read directly from DASD and, as a result, can be supplied to the channel at the speed associated with electronic storage rather than that of magnetic storage.
For read operations data can be transferred between the cache and channel at channel speeds which can often be as high as 18 MB per second, depending upon the host processor, cache and channel configurations. In addition, as will be explained later, it is also possible to accept and process write operations originating from the channel at greatly improved speeds through the use of cache.
With the benefit of caching read operations recognized, designers, intent upon further improving system performance, turned to write operation caching to supplement the previously described read caching operations. Write caching, however, involves a data integrity problem not present when caching data for a subsequent read operation. In the event of a power loss to the cache, cache memory being volatile, data residing in the cache memory will be lost. Thus it is apparent that a backup copy of cached data is necessary if write operation caching is desired.
Recognizing this problem, designers, such as those involved with the IBM 3990 DASD Controller, added non-volatile storage (NVS) to the controller hardware. The NVS memory array is supported by a battery backup system that can maintain the data in the NVS for a finite period of time after power failure. In the event of a power failure, any data residing in nonvolatile storage is written to DASD, at the time power is restored, under the direction of the DASD controller.
Cached write operations, as well as the above mentioned read operations are now described. Cache operations take four basic forms. The first of these forms is termed subsystem caching or read only caching. This type of caching allows direct transfer of data from the cache, if the data is present in the cache, to the channel. This situation is known as a "read hit". If the data requested by the channel is not present in the cache, a "read miss" occurs and the data must be retrieved from the DASD device. When this happens, the data is concurrently written to cache in anticipation of future requests for that data. In addition, the data present from the requested record to the end of the DASD track is copied into cache.
The second cache operation is a "DASD fast write". This operation, unlike subsystem caching, is a write operation. As with any cached write operation, DASD fast write requires an NVS backup, associated with the cache memory to prevent data loss in the event of a power failure. DASD fast write allows for faster write operation processing in that access to the DASD device is not necessary if the data is present in cache. If it so happens that the data to be written is present in the cache, instead of writing the data update to DASD, the storage director copies the data received from the channel into cache and NVS. Once this is done, the storage director can return channel end and device end status.
In this manner host processing can continue without waiting for the data to be placed on DASD. The data is not actually written to DASD until it is necessary to free space in the cache or NVS. If the data is not present in the cache, then a "write miss" occurs and the data is written to DASD and to cache simultaneously and immediately. In addition, the remainder of the track containing the record to be written is staged to cache for future anticipated use.
A third cache operation is known as "cache fast write". It is quite similar to DASD fast write except that data is never written to NVS and in many situations data is never written to DASD. Cache fast write is primarily intended for data that is not required at job completion (e.g. sorting files using intermediate work files) or data that can be reconstructed easily. Cache fast write is typically enabled through program modification in contrast to DASD fast write which can be activated through a system utility command.
The fourth basic cache operation is dual copy. Dual copy allows for the creation of a second, duplicate copy of data on a different device within the storage subsystem. Dual copy is typically used with critical data as protection against a single device failure. In case of a primary device failure, data transfer operations are switched automatically to the secondary device in a manner transparent to the application program.
Dual copy treats a write in much the same manner as a standard write operation. Once data has been written to the primary volume, the storage control sends a channel-end and device-end status to the channel (allowing the host to continue processing) and then writes the data to cache and its associated control information to NVS. The data is then written to the secondary volume. Data is read only from the primary volume unless a device failure makes it necessary to use the secondary volume.
With the obvious advantages of caching in mind, it can be recognized that a system will achieve optimum performance by implementing the caching operations at all times. However, this is not possible in the event of certain system failures. In order to address this problem, controller designs have provided for multiple power partitions, each partition containing one or more subsystem components. As an example, the IBM 3990 Model 3 contains two storage clusters, each containing two paths to DASD peripherals such as a string of IBM 3390 DASDs. Each storage cluster is contained within its own power and service boundary. Moreover, the IBM 3990 Model 3 includes one cache and one NVS each shared by all four storage paths in the subsystem and each having its own power supply.
Thus a failure causing the loss of one of the clusters will permit the other cluster to continue functioning and allow for two storage paths between DASD and the host processor. However, if the single cache memory only is lost, the subsystem can continue to operate only by transferring data directly between DASD and the channel. Thus, an overall degradation of system performance will occur should this single point of failure occur.
It has been recognized that cached read and/or write operations within the DASD controller could continue even in the face of cache failure if one or more additional cache arrays are provided. In order to maintain the extended caching function, however, it is necessary that the additional caches be located in a separate power region from the first cache and preferably from all other subsystem components.
It is further desirable to include an additional NVS shadowing each additional cache memory and to include them in separate power regions as well. While additional cache arrays could be added without a corresponding shadow NVS, this would require NVS sharing among cache arrays and would allow a single point of failure for some cache functions such as DASD fast write.
The person of ordinary skill in the art will recognize that the addition of multiple memory elements requires a control mechanism to differentiate among them in the case of data transfers. This is especially so since each of the multiples caches and each of the multiple NVSs used in the storage controller will use the same address as far a the microcontroller is concerned. Furthermore, additional microcode logic to implement this function can be costly in terms of subsystem efficiency. In addition, an implementation using additional microcode logic introduces the possibility for logic defects and thus subsystem failures.